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Socrates Wong is a PhD candidate in Electrical and Computer Engineering at Cornell University specializing in high-performance computer architecture. He has a passion for “making the numbers go up,” whether through software optimizations, hardware design, processing-in-memory (PIM), associative processors, or hybrid emerging-technology architectures. He has developed several generations of associative processors—including Hybrid CAPE, and PUMICE—achieving substantial improvements such as 28.4× faster addition, and 22.5× faster multiplication. His work accelerates workloads in ML, genomics, cryptography, and large-model inference. He holds dual bachelor’s degrees in Computer Engineering and Computer & Information Technology from Purdue University.
Socrates Wong is a PhD candidate in Electrical and Computer Engineering at Cornell University specializing in high-performance computer architecture. He has a passion for “making the numbers go up,” whether through software optimizations, hardware design, processing-in-memory (PIM), associative processors, or hybrid emerging-technology architectures. He has developed several generations of associative processors—including Hybrid CAPE, and PUMICE—achieving substantial improvements such as 28.4× faster addition, and 22.5× faster multiplication. His work accelerates workloads in ML, genomics, cryptography, and large-model inference. He holds dual bachelor’s degrees in Computer Engineering and Computer & Information Technology from Purdue University.
He is currently seeking full time employment following his planned defense on December 2025
Education
Education
PhD in Electrical and Computer Engineering | Anticipated Degree Date May 2025 | Cornell University
PhD in Electrical and Computer Engineering | Anticipated Degree Date May 2025 | Cornell University
· Advisor: Professor José F. Martínez
· Planned Defense: December 2025
Masters of Science in Electrical and Computer Engineering | May 2023| Cornell University
Masters of Science in Electrical and Computer Engineering | May 2023| Cornell University
BS in Computer Engineering | May 2019 | Purdue University
BS in Computer Engineering | May 2019 | Purdue University
Bs in Computer Information Technology | May 2019 | Purdue University
Bs in Computer Information Technology | May 2019 | Purdue University
Research Interest
Research Interest
Computer Architecture, High Performance Computation, ML, LLM, Compilers, NLP, RISC-V
Computer Architecture, High Performance Computation, ML, LLM, Compilers, NLP, RISC-V
The AP Saga (Dissertation)
The AP Saga (Dissertation)
PUMICE — Tightly Integrated CPU-PUM Architecture
PUMICE — Tightly Integrated CPU-PUM Architecture
· Designed a tightly integrated CPU–PUM system exploiting both ILP and DLP for long-vector execution.
· Designed a tightly integrated CPU–PUM system exploiting both ILP and DLP for long-vector execution.
· Delivered up to 2.2× speedup (1.4× average) relative to decoupled PUM architectures.
· Delivered up to 2.2× speedup (1.4× average) relative to decoupled PUM architectures.
· Created a unified execution model enabling scalar–vector symbiosis.
· Created a unified execution model enabling scalar–vector symbiosis.
Hybrid CAPE — FeFET/CMOS hybrid PIM architecture
Hybrid CAPE — FeFET/CMOS hybrid PIM architecture
· Developed a hybrid FeFET–CMOS associative processor
· Developed a hybrid FeFET–CMOS associative processor
· Achieved 30% area and 11% energy savings with only 1% performance loss vs CMOS-only designs.
· Achieved 30% area and 11% energy savings with only 1% performance loss vs CMOS-only designs.
· Built detailed spice + architecture models showing significant endurance improvements over pure FeFET solutions.
· Built detailed spice + architecture models showing significant endurance improvements over pure FeFET solutions.
Research Experience
Research Experience
Graduate Researcher | 2019-Present
Graduate Researcher | 2019-Present
CSL, Cornell University, Ithaca, NY
CSL, Cornell University, Ithaca, NY
Undergrad Researcher | 2018-2019
Undergrad Researcher | 2018-2019
Purdue University, West Lafayette, IN
Purdue University, West Lafayette, IN
Publications
Publications
S. Wong, C. Tamarit, D. Reis, M. Niemier, X. Hu, J. Martínez (2026). A Hybrid Approach to Emerging Memory Technology-based Processing-in-Memory Architectures. Appeared in DATE’26
S. Wong, C. Tamarit, J. Martínez (2023). PUMICE: Processing-using-Memory Integration with a Scalar Pipeline for Symbiotic Execution. Appeared in DAC’23
Leadership & Service
Leadership & Service
ECE Peer Mentor Program | 2024-2025
ISCA Artifact Evaluation | 2024
CSL Student Steering Committee | 2020-2023
Floor Rep for Residence Hall’s Titian Club | 2015-2019
Purdue Student Government’s Board of Director | 2015-2016
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